Below is a frequency multiplier based around a step recovery diode (SRD). The input frequency is 1.6 GHz and the output frequency is 9.6 GHz. The PCB & schematic were generated in Altium Designer, the layout was then imported into HFSS for characterization. HFSS provided a 29 port s-parameter file for the harmonic balance simulation (ADS). Separately, the edge coupled filter was modified & optimized using HFSS. The filter uses four half-wave resonators – but the method of coupling is different in this design eliminating very narrow gaps (making the design manufacturable).